Sfoglia per Autore
An Efficient Simple Algorithm for Fault Tree Automatic Synthesis from the Reliability Graph
1978-01-01 Camarda, P.; Corsi, F.; Trentadue, A.
An Efficient Simple Algorithm for the Automatic Synthesis of Fault Trees
1978-01-01 Corsi, Francesco; Camarda, Pietro; Trentadue, A.
Optical Fiber Computer Network Design
1979-01-01 Bozzetti, Michele; Camarda, Pietro; Corsi, Francesco; R., De Leo
RELIABILITY TEST PLAN FOR A PROTECTIVE EQUIPMENT
1979-01-01 Corsi, Francesco; Murgolo, F; Savino, M; SYLOS LABINI, M; Tantalo, P.
NON LINEARLY LOADED INSULATED PROBES FOR THE MEASUREMENT OF ELECTRICAL FIELD DISTRIBUTION IN BIOLOGICAL MEDIA
1980-01-01 Corsi, Francesco; Bozzetti, Michele; DE LEO, R.
AN AVAILABILITY EVELUATION FOR COMPUTER COMMUNICATION NETWORKS
1980-01-01 Corsi, Francesco; DE LEO, R.
Electromagnetic coupling between apertures and biological structures
1981-01-01 Bozzetti, M.; Corsi, F.; De Leo, R.
QUEUE LENGHT PDF ESTIMATION IN SLOTTED CHANNEL COMPUTER NETWORKS
1982-01-01 Corsi, Francesco; D'Agostino, V.
A review of RAM testing methodologies
1983-01-01 Corsi, F.; Morandi, C.
PROBABILISTIC DELAY EVALUATION IN COMBINATIONAL CIRCUITS BY PETRI NETS
1983-01-01 Corsi, Francesco; Castagnolo, B.
Mathematical models for marginal reliability analysis
1983-01-01 Corsi, Francesco
Modelling digital circuits with delays by Stochastic Petri Nets
1983-01-01 Castagnolo, B.; Corsi, F.
AN EFFICIENT LOGIC SIMULATOR FOR VLSI CIRCUITS BASED ON PETRI NETS
1984-01-01 Corsi, Francesco; Castagnolo, B; Fortunato, I; Gubian, P.
COMPUTATIONAL COMPLEXITY OF 2-D IMAGE PROCESSING BY A PARALLEL ARCHITECTURE
1984-01-01 Corsi, Francesco; Castagnolo, B; Larizza, P; Pascoschi, G.
A MICROPROCESSOR CONTROLLED RELIABLE HIGH PRECISION GONIOMETER
1984-01-01 Corsi, Francesco; Cimaglia, G; Guerci, J. C.
Multistate Markov Models and Structural Properties of the Transition-Rate Matrix
1986-01-01 Cafaro, Giuseppe; Corsi, Francesco; Vacca, Francesco
Evaluation of the Behaviour of Digital Circuits by Timed Petri Nets
1986-01-01 Castagnolo, B.; Corsi, F.
PROBABILISTIC TESTABILITY ANALYSIS OF LOGIC CIRCUITS
1987-01-01 Corsi, Francesco
A 2-D FFT PROCESSOR IN 3 UM CMOS TECHNOLOGY
1987-01-01 Corsi, Francesco; Castagnolo, B; Di Lecce, Vincenzo
LOGIC TESTABILITY ANALYSIS USING BIPARTITE GRAPHS
1987-01-01 Corsi, Francesco; Castagnolo, B.
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