A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications / Ciciriello, F.; Altieri, Pr.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, Lorenzo; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - ELETTRONICO. - 12:11(2017). [10.1088/1748-0221/12/11/T11005]

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

Ciciriello, F.;Corsi, F.;Lorusso, Lorenzo;Marzocca, C.
;
Matarrese, G.;
2017-01-01

Abstract

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.
2017
A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications / Ciciriello, F.; Altieri, Pr.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, Lorenzo; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - ELETTRONICO. - 12:11(2017). [10.1088/1748-0221/12/11/T11005]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11589/122932
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