A logic simulation tool called PENELOPE (Petri net logic performance evaluator) with precise delay estimation capabilities is presented. The simulator, which is particularly intended for CMOS circuits, makes use of a description of the logic network in terms of a Petri-net-like graph which implements the truth table of each logic operator and also processes the property of describing the evolution of the signal transitions in the network. Comparisons are made with other known simulators, showing that the performances are quite interesting especially in view of the precise modelling of time delays in the network
PENELOPE: a graph based logic simulator for MOS circuits / Castagnolo, B.; Corsi, F.; Martino, S.. - In: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS PROCEEDINGS. - ISSN 0271-4302. - STAMPA. - (1988), pp. 1365-1368. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems, ISCAS 1988 tenutosi a Espoo, Finland nel June 7-9 , 1988) [10.1109/ISCAS.1988.15182].
PENELOPE: a graph based logic simulator for MOS circuits
Castagnolo, B.;Corsi, F.;
1988-01-01
Abstract
A logic simulation tool called PENELOPE (Petri net logic performance evaluator) with precise delay estimation capabilities is presented. The simulator, which is particularly intended for CMOS circuits, makes use of a description of the logic network in terms of a Petri-net-like graph which implements the truth table of each logic operator and also processes the property of describing the evolution of the signal transitions in the network. Comparisons are made with other known simulators, showing that the performances are quite interesting especially in view of the precise modelling of time delays in the networkI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
