This paper presents the analysis and optimization of a cheap polynomial fitting method for built-in Analog to Digital Converters testing. Optimization has been carried on using a high-level mixed-signal cosimulation and codesign tool called CodeSimulink. Measurements have validated the high-level model, which therefore proved to be reliable. The optimization carried on by using the proposed approach, allowed to reach the same accuracy (≈90dB) achieved by the more expensive FFT-based test strategy. The high-level model has then been automatically converted into a VHDL file, which can then be compiled to either FPGA or buitl-in as an ASIC into the converter itself
High-level optimization of built-in self test for analog to digital converters / DE VENUTO, Daniela; Reyneri, L.. - (2006), pp. 101-104. (Intervento presentato al convegno 13th IEEE Mediterranean Electrotechnical Conference, MELECON 2006 tenutosi a Malaga, Spain nel May 16-19, 2006) [10.1109/MELCON.2006.1653046].
High-level optimization of built-in self test for analog to digital converters
DE VENUTO, Daniela;
2006-01-01
Abstract
This paper presents the analysis and optimization of a cheap polynomial fitting method for built-in Analog to Digital Converters testing. Optimization has been carried on using a high-level mixed-signal cosimulation and codesign tool called CodeSimulink. Measurements have validated the high-level model, which therefore proved to be reliable. The optimization carried on by using the proposed approach, allowed to reach the same accuracy (≈90dB) achieved by the more expensive FFT-based test strategy. The high-level model has then been automatically converted into a VHDL file, which can then be compiled to either FPGA or buitl-in as an ASIC into the converter itselfI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
