Design of High Speed Circuits for Systematic Cyclic Error Correction Codes

In this paper the design of an encoder and of a decoder for systematic Hamming codes is carried out. Full-parallel architecture is used and hardware is easy to implement, being composed of a cascade of combinational equal structures. The proposed solution allows high bit rates and high degree of modularity, so an easy integration of the circuits is possible. These characteristics make the method suitable to be adopted in a photonic environment in which clocked digital memory elements are still a critical aspect. The methodology, employed to synthesize Hamming code circuits, has a general validity: in fact, it can be adopted for every systematic cyclic code.