In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.
A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis / Gelao, Gennaro; Marani, Roberto; Pizzulli, Luciano; Perri, Anna Gina. - In: CURRENT NANOSCIENCE. - ISSN 1573-4137. - STAMPA. - 11:4(2015), pp. 515-526. [10.2174/1573413711666150320231414]
A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis
Gelao, GennaroSoftware
;Marani, RobertoMethodology
;Perri, Anna Gina
Conceptualization
2015-01-01
Abstract
In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.File in questo prodotto:
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