An in detail design of digital window comparators is presented. This comparator can be used for the on-chip (and potentially on-line) response evaluation of analogue circuits. The analysis shows that if the design parameter β is in the order of 1 . . . 0,36 for the NOR and 1 . . . 2,8 for the NAND good results for the comparator can be achieved and the variation of the window position is limited to 5%. Parameter and temperature drifts are discussed along with results from characterisation. The results can be extended to deep-submicron technologies if the respective equations are used to derive the logical threshold and beta values. A simplified comparator is described that also allows the localisation of the evaluated signal. The conditions for the implementation of the window comparators into Design-for-Testability schemes are outlined. It is demonstrated that the digital window comparator can be implemented in the digital part of the mixed-signal integrated circuit.
|Titolo:||Design of Digital Window Comparators and their Implementation within Mixed-Signal DfT Schemes|
|Data di pubblicazione:||2003|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1023/A:1024178515942|
|Appare nelle tipologie:||1.1 Articolo in rivista|