Main stream bulk CMOS and the variants of silicon-on-insulator (SOI) CMOS technologies are discussed with respect to testing for the quiescent current of mixed-signal integrated SOI circuits. The 2-3 times lower static power consumption in fully depleted CMOS/SOI compared to bulk CMOS allows quiescent current testing also for high performance analogue circuits at an acceptable defect resolutions. From first simulations and technological considerations, it turned out that quiescent current tests are able to detect not only commonly known defects, but also SOI specific defects such as self-heating, kink-effect or the parasitic bipolar behaviour. It is further shown that in partially depleted thick-film SOL the kink-effect and parasitic bipolar transistor support the quiescent current test for some specific defects as they elevate the defective quiescent current level. In fully depleted kink-free SOI circuits, the kink-effect may occur due to process failures but then can be detected by quiescent current tests. A special fault simulation model for the kink-effect is presented. The I-ccq test technique is studied for a CMOS/SOI Miller operational amplifier. Normal 6-sigma variation of the aspect ratio and the threshold voltage do not jeopardise the defect detection in the quiescent current. First, results confirm the good detection capabilities of the quiescent current test, in particular, of failures which are not visible in the output voltage.
|Titolo:||Fault detection in CMOS/SOI mixed-signal circuits using the quiescent current test|
|Data di pubblicazione:||2002|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1016/S0026-2692(02)00008-3|
|Appare nelle tipologie:||1.1 Articolo in rivista|