The implementation of a decoder for cyclic redundancy check codes at very high bit rates is suggested. it is based on a purely combinational, iterative cells circuit. The theoretical performance evaluation and the simulations show the enhancement in terms of operating speed with respect to the sequential solution.

High-speed error correction circuit based on iterative cells / Castagnolo, B.; Rizzi, M.. - In: INTERNATIONAL JOURNAL OF ELECTRONICS. - ISSN 0020-7217. - STAMPA. - 14:4(1993), pp. 529-540. [10.1080/00207219308925856]

High-speed error correction circuit based on iterative cells

Castagnolo, B.;Rizzi, M.
1993-01-01

Abstract

The implementation of a decoder for cyclic redundancy check codes at very high bit rates is suggested. it is based on a purely combinational, iterative cells circuit. The theoretical performance evaluation and the simulations show the enhancement in terms of operating speed with respect to the sequential solution.
1993
High-speed error correction circuit based on iterative cells / Castagnolo, B.; Rizzi, M.. - In: INTERNATIONAL JOURNAL OF ELECTRONICS. - ISSN 0020-7217. - STAMPA. - 14:4(1993), pp. 529-540. [10.1080/00207219308925856]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11589/11603
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