This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC. A 64 à 64 matrix of 50 à 50 μ m2pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm2pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.
A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC / Monteil, E.; Pacher, L.; Paternò, A.; Loddo, F.; Demaria, N.; Gaioni, L.; De Canio, F.; Traversi, G.; Re, V.; Ratti, L.; Rivetti, A.; Da Rocha Rolo, M.; Dellacasa, G.; Mazza, G.; Marzocca, C.; Licciulli, F.; Ciciriello, F.; Marconi, S.; Placidi, P.; Magazzù, G.; Stabile, A.; Mattiazzo, S.; Veri, C.. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - 11:12(2016). [10.1088/1748-0221/11/12/C12044]
A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC
Re, V.;Marzocca, C.;Licciulli, F.;Ciciriello, F.;
2016-01-01
Abstract
This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC. A 64 à 64 matrix of 50 à 50 μ m2pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm2pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
