This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC / Paternò, A., Pacher, L., Monteil, E., Loddo, F., Demaria, N., Gaioni, L., De Canio, F., Traversi, G., Re, V., Ratti, L., Rivetti, A., Da Rocha Rolo, M., Dellacasa, G., Mazza, G., Marzocca, C., Licciulli, F., Ciciriello, F., Marconi, S., Placidi, P., Magazzu, G., et al.. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - 12:2(2017). [10.1088/1748-0221/12/02/C02043]

A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

Marzocca, C.;Licciulli, F.;Ciciriello, F.;
2017

Abstract

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.
2017
http://iopscience.iop.org/article/10.1088/1748-0221/12/02/C02043/meta
A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC / Paternò, A., Pacher, L., Monteil, E., Loddo, F., Demaria, N., Gaioni, L., De Canio, F., Traversi, G., Re, V., Ratti, L., Rivetti, A., Da Rocha Rolo, M., Dellacasa, G., Mazza, G., Marzocca, C., Licciulli, F., Ciciriello, F., Marconi, S., Placidi, P., Magazzu, G., et al.. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - 12:2(2017). [10.1088/1748-0221/12/02/C02043]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11589/116621
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