In the framework of the CHIPIX65 project, that aims at prototyping a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC, a 12-bit ADC has been designed for monitoring slowly varying signals and dc voltage reference levels. The architecture of the ADC is based on a dual-slope integrating structure and the circuit has a 460umx275um area. All the analog blocks have been placed in a deep n-well for better rejecting noise coming from the digital part. In addition, an innovative self-calibration procedure has been implemented in hardware to set the internal configuration registers of the ADC, which control its configurable parameters, as soon as the circuit is powered up. Two versions of the ADC have been prototyped and the second one has been also integrated in the CHIPIX65 demonstrator ASIC. First measurement tests have been carried out to validate the performance of the circuit in terms of linearity and resolution.
Attenzione! Scheda prodotto non ancora validata
I metadati della pubblicazione sono in fase di verifica da parte dell'Ateneo
|Titolo:||A Rad-Hard 12-bit Auto-Calibrated ADC in CMOS 65nm|
|Data di pubblicazione:||9999|
|Nome del convegno:||Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD), 2016|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|