This paper proposes a design-oriented approach for Class E power amplifier drain efficiency maximization. The proposed approach merges the versatility of the State Space circuits' description, with the numerical convergence to the Class E optimal working conditions by a transient analysis. The tool provides an automatic optimization of the Class E components, just by inserting the design specifications and the starting values. The second step of the automatic iterative tuning allows preserving the highest value of power efficiency. All specifications realize a three-dimensional matrix, which allows converging (with 60 iterations in about 3s) to an optimal solution by using the crosscheck of the specifications. Finally, as case study, an η-optimal design has been implemented by using the proposed tool. We compare the analytical design of the Class E PA implemented in TSMC 65nm CMOS technology, with the State Space Model technique here described. The new design reaches an efficiency of 87% in simulation, with an η increment of 12% respect the original design.
State Space Model-Oriented Design for Efficiency Improvement of Class-E Power Amplifier / De Venuto, Daniela; Mezzina, Giovanni. - ELETTRONICO. - (2018), pp. 65-68. (Intervento presentato al convegno 2018 International Conference on IC Design and Technology, ICICDT 2018 tenutosi a Otranto, Italy nel June 4-6, 2018) [10.1109/ICICDT.2018.8399757].
State Space Model-Oriented Design for Efficiency Improvement of Class-E Power Amplifier
De Venuto, Daniela
;Mezzina, Giovanni
2018-01-01
Abstract
This paper proposes a design-oriented approach for Class E power amplifier drain efficiency maximization. The proposed approach merges the versatility of the State Space circuits' description, with the numerical convergence to the Class E optimal working conditions by a transient analysis. The tool provides an automatic optimization of the Class E components, just by inserting the design specifications and the starting values. The second step of the automatic iterative tuning allows preserving the highest value of power efficiency. All specifications realize a three-dimensional matrix, which allows converging (with 60 iterations in about 3s) to an optimal solution by using the crosscheck of the specifications. Finally, as case study, an η-optimal design has been implemented by using the proposed tool. We compare the analytical design of the Class E PA implemented in TSMC 65nm CMOS technology, with the State Space Model technique here described. The new design reaches an efficiency of 87% in simulation, with an η increment of 12% respect the original design.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.