The possibility of using window comparators for on-chip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored on by the application. With this approach, test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected.
|Titolo:||On-Chip Signal Level Evaluation for Mixed-Signal ICs using Digital Window Comparators|
|Data di pubblicazione:||2001|
|Nome del convegno:||IEEE European Test Workshop, ETW 2001|
|Digital Object Identifier (DOI):||10.1109/ETW.2001.946664|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|