In this paper, we propose two scalable architectures (called ArcJ and Arc*2) which perform the Discrete Wavelet Transform (DWT) of an N0-sample sequence in only N0/2 clock cycles. Therefore, they are at least twice as fast as the known architectures. Also, their AT2 parameter is approximately 1/2 of that of already existing devices. These results allow either a twice faster processing than that allowed by other architectures working at the same clock frequency (High-Speed utilization), or using a twice lower clock frequency, while reaching the same performance as other architectures. This second possibility permits reducing the power dissipation by a factor of 4 with respect to other architectures (Low-Power utilization). Finally, we shall show that an impressively efficient architecture can be defined as the synthesis of ArcJ and Arc*2 (average efficiency = 99.1%, minimum efficiency = 93.8%).
|Titolo:||High-Speed/Low-Power 1-D DWT Architectures with High Efficiency|
|Data di pubblicazione:||2000|
|Nome del convegno:||IEEE International Symposium on Circuits and Systems, ISCAS 2000|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1109/ISCAS.2000.857433|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|