A design-for-testability implementation to achieve high fault coverages in the analogue functional blocks of mixed circuit ASICs is presented in this feasibility study. To this end existing op amps or OTAs are converted into clocked comparators with hysteresis and variable reference levels. The resulting two-mode comparators are connected to specific internal nodes. Depending on the mode this node can be either statically and/or dynamically evaluated on-chip without the need to bring an analogue signal off-chip. Results from first simulations and measurements on a test circuit realised in 0.35 /spl mu/m technology are presented
Static and dynamic on-chip test response evaluation using a two-mode comparator / DE VENUTO, Daniela; M. J., Ohletz; Matarrese, Gianvito. - (2000), pp. 47-52. (Intervento presentato al convegno IEEE European Test Workshop, ETW'00 tenutosi a Cascais, Portugal nel May 23-26, 2000) [10.1109/ETW.2000.873778].
Static and dynamic on-chip test response evaluation using a two-mode comparator
DE VENUTO, Daniela;MATARRESE, Gianvito
2000-01-01
Abstract
A design-for-testability implementation to achieve high fault coverages in the analogue functional blocks of mixed circuit ASICs is presented in this feasibility study. To this end existing op amps or OTAs are converted into clocked comparators with hysteresis and variable reference levels. The resulting two-mode comparators are connected to specific internal nodes. Depending on the mode this node can be either statically and/or dynamically evaluated on-chip without the need to bring an analogue signal off-chip. Results from first simulations and measurements on a test circuit realised in 0.35 /spl mu/m technology are presentedI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
