A new technique is proposed here to increase the output impedance of a MOS current source, well suited to be used, for instance, as tail current for differential pairs. Operation at very low output voltage levels is possible, since the technique is not based on the application of series negative feedback schemes to the output current. The compliance voltage of the source is limited to the VDSAT of a single MOS transistor. SPICE simulations confirm the effectiveness of the technique, which allows to achieve output impedances of the same order of magnitude of cascoded current mirrors without using output transistors with large lengths, thus minimizing also the total capacitance seen at the output node.
A Low Voltage, High Output Impedance CMOS Current Source / Di Ciano, M.; Marzocca, Cristoforo; Tauro, A.. - (2004), pp. 237-241. (Intervento presentato al convegno IEEE International Conference on Semiconductor Electronics, ICSE 2004 tenutosi a Kuala Lumpur, Malaysia nel December 4-9, 2004) [10.1109/SMELEC.2004.1620878].
A Low Voltage, High Output Impedance CMOS Current Source
MARZOCCA, Cristoforo;
2004-01-01
Abstract
A new technique is proposed here to increase the output impedance of a MOS current source, well suited to be used, for instance, as tail current for differential pairs. Operation at very low output voltage levels is possible, since the technique is not based on the application of series negative feedback schemes to the output current. The compliance voltage of the source is limited to the VDSAT of a single MOS transistor. SPICE simulations confirm the effectiveness of the technique, which allows to achieve output impedances of the same order of magnitude of cascoded current mirrors without using output transistors with large lengths, thus minimizing also the total capacitance seen at the output node.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
