The possibility of using window comparators for on-chip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored to the application. With this approach, the test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected.
Testing of Analogue Circuits via (Standard) Digital Gates / De Venuto, D.; Ohletz, M. J.; Ricco, B.. - STAMPA. - (2002), pp. 112-119. (Intervento presentato al convegno 3rd International Symposium on Quality Electronic Design, ISQED 2002 tenutosi a San Jose, CA nel March 18-21, 2002) [10.1109/ISQED.2002.996709].
Testing of Analogue Circuits via (Standard) Digital Gates
D. De Venuto;
2002-01-01
Abstract
The possibility of using window comparators for on-chip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored to the application. With this approach, the test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
