A hardware architecture for on-line three dimensional backprojection is considered for positron emission tomography (PET). The architecture is based on processing elements that work in pipeline on a flowing data stream using an event by event approach. The architecture is suitable for backprojection filtering reconstruction where reconstruction requires backprojection first and a subsequent three-dimensional filtering. Although the main target of the architectural design is a VLSI implementation, the modularity of the approach also makes it suitable for an implementation on off the shelf processors. The work takes as reference the complexity requirements of a PET scanner endowed of 24 rings and 784 detectors per ring and a volume of interest subdivided into 128*128*47 voxels. The design of the building blocks of the architecture are described together with their operating mode.
A Pipeline backprojector for on-line 3-D PET / Di Lecce, V.; Di Sciascio, E.; Manni, A. R.. - STAMPA. - (1996), pp. 1069-1073. (Intervento presentato al convegno IEEE Nuclear Science Symposium and Medical Imaging Conference, 1995 tenutosi a San Francisco, CA nel October 21-28, 1995) [10.1109/NSSMIC.1995.510449].
A Pipeline backprojector for on-line 3-D PET
V. Di Lecce;E. Di Sciascio;
1996-01-01
Abstract
A hardware architecture for on-line three dimensional backprojection is considered for positron emission tomography (PET). The architecture is based on processing elements that work in pipeline on a flowing data stream using an event by event approach. The architecture is suitable for backprojection filtering reconstruction where reconstruction requires backprojection first and a subsequent three-dimensional filtering. Although the main target of the architectural design is a VLSI implementation, the modularity of the approach also makes it suitable for an implementation on off the shelf processors. The work takes as reference the complexity requirements of a PET scanner endowed of 24 rings and 784 detectors per ring and a volume of interest subdivided into 128*128*47 voxels. The design of the building blocks of the architecture are described together with their operating mode.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
