In this paper we present a study of the impact of technology on the CNTFET-based circuits performance. In particular we show the layout of a NOT gate, used as block to build a chain of NOT and a ring oscillator. Then we present the time domain simulations of these circuits in order to see how the parasitic elements could limit the high-speed performances of CNTFETs.
Impact of Technology on CNTFET-based Circuits Performance / Marani, Roberto; Perri, Anna Gina. - In: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY. - ISSN 2162-8777. - STAMPA. - 9:5(2020). [10.1149/2162-8777/ab9185]
Impact of Technology on CNTFET-based Circuits Performance
Marani, RobertoSoftware
;Perri, Anna Gina
Conceptualization
2020
Abstract
In this paper we present a study of the impact of technology on the CNTFET-based circuits performance. In particular we show the layout of a NOT gate, used as block to build a chain of NOT and a ring oscillator. Then we present the time domain simulations of these circuits in order to see how the parasitic elements could limit the high-speed performances of CNTFETs.File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
