The design and first measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optmised for the lowest power consumption. The proposed design has a power consumption of 0.52μW at a bitclock of 50-kHz and of 0.85μW at 100-kHz with a 1.2-V supply. As far as we know, the Figure-of-Merit of 66 fJ/convertion-step is the best reported so far. The ADC was realised in the NXP CMOS 0.14μm technology with an area of 0.35 mm 2. Only four metal layers were used in order to allow 3D integration of the sensors
Ultra Low-Power 12-bit SAR ADC for RFID Applications / DE VENUTO, Daniela; Stikvoort, E.; Tio Castro, D.; Ponomarev, Y.. - (2010), pp. 1071-1075. (Intervento presentato al convegno Design, Automation & Test in Europe Conference & Exhibition, DATE 2010 tenutosi a Dresden, Germany nel March 8-12, 2010).
Ultra Low-Power 12-bit SAR ADC for RFID Applications
DE VENUTO, Daniela;
2010-01-01
Abstract
The design and first measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optmised for the lowest power consumption. The proposed design has a power consumption of 0.52μW at a bitclock of 50-kHz and of 0.85μW at 100-kHz with a 1.2-V supply. As far as we know, the Figure-of-Merit of 66 fJ/convertion-step is the best reported so far. The ADC was realised in the NXP CMOS 0.14μm technology with an area of 0.35 mm 2. Only four metal layers were used in order to allow 3D integration of the sensorsI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
