Design strategies for power effective and high resolution Successive-Approximation ADCs for autonomous multisensor systems are discussed. Specifically, an optimisation for lowest possible power consumption of comparators is addressed and evaluated using both simulations and measurements of a fabricated Si testchip. The proposed design solution is capable to provide a 12-bit resolution at 50-kHz with only 0.1uW power consumption on a 1.2-V supply. The achieved Figure-of- Merit is 165 fJ/convertion-step is, to our knowledge, the best ever reported. The complete ADC area is 0.35 mm2 in NXP 0.14um CMOS technology with only three metal layers
Low Power 12-bit SAR ADC for Autonomous Wireless Sensors Network Interface / DE VENUTO, Daniela; Castro, D. T.; Ponomarev, Y.; Stikvoort, E.. - (2009), pp. 115-120. (Intervento presentato al convegno 3rd International Workshop on Advances in Sensors and Interfaces, IWASI 2009 tenutosi a Trani, Italy nel 25-26 June 2009) [10.1109/IWASI.2009.5184780].
Low Power 12-bit SAR ADC for Autonomous Wireless Sensors Network Interface
DE VENUTO, Daniela;
2009-01-01
Abstract
Design strategies for power effective and high resolution Successive-Approximation ADCs for autonomous multisensor systems are discussed. Specifically, an optimisation for lowest possible power consumption of comparators is addressed and evaluated using both simulations and measurements of a fabricated Si testchip. The proposed design solution is capable to provide a 12-bit resolution at 50-kHz with only 0.1uW power consumption on a 1.2-V supply. The achieved Figure-of- Merit is 165 fJ/convertion-step is, to our knowledge, the best ever reported. The complete ADC area is 0.35 mm2 in NXP 0.14um CMOS technology with only three metal layersI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
