A novel design and measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optimised for the lowest power consumption. The proposed design has a power consumption of 0.52μW at a bitclock of 50-kHz and of 0.85μW at 100-kHz with a 1.2-V supply. The Figure-of-Merit reached with such implementation is of 66 fJ/conversion-step. The ADC was realised in the NXP CMOS 0.14μm technology with an area of 0.35 mm2. Only four metal layers were used in order to allow 3D integration of the sensors.
Novel low-power 12-bit SAR ADC for RFID tags / De Venuto, Daniela; Stikvoort, Eduard; Tio Castro, David; Ponomarev, Youri. - ELETTRONICO. - (2010), pp. 532-537. (Intervento presentato al convegno 11th International Symposium on Quality Electronic Design, ISQED 2010 tenutosi a San Josè, CA nel March 22-24, 2010) [10.1109/ISQED.2010.5450523].
Novel low-power 12-bit SAR ADC for RFID tags
Daniela De Venuto;
2010-01-01
Abstract
A novel design and measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optimised for the lowest power consumption. The proposed design has a power consumption of 0.52μW at a bitclock of 50-kHz and of 0.85μW at 100-kHz with a 1.2-V supply. The Figure-of-Merit reached with such implementation is of 66 fJ/conversion-step. The ADC was realised in the NXP CMOS 0.14μm technology with an area of 0.35 mm2. Only four metal layers were used in order to allow 3D integration of the sensors.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
