A VLSI ‘rest’ processing element with improved bus connections (an evaluation)

A highly parallel architecture based on ‘’ type processor elements () and designed to make good use of Very Large Scale Integration technology is proposed. The system is realized with 512 : the special structure of the single , each provided with the proper control firmware, allows to specialize, in the bootstrap phase, the functionality, implementing dynamically both and structures. The layout of a C-mos transmission-gate, for a special sub-unit (su), is presented. The single-cell transmission-gate, realized with 3 um technology, has a dimension of 68 um. The propagation time evaluation for the single cell is 3.2 us. As an example of the use of this structure the algorithm for computing the product of a 512∗512 matrix by a vector of 512 elements is also shown: the execution time for this algorithm is about 1 ms.