An application-specific array processing chip has been designed to be the basic element of a massively parallel fine-grained architecture that has been developed for FFT processing in SAR data evaluation. The chip integrates 160 bit-serial processing elements that can perform 80 bufferfly operations in parallel. Each serial processing element is extremely compact, and needs very little control. Operands can have both fixed point and floating point sign magnitude format; hardware solutions adopted allow the computation in totally pipelined mode. 2 μm CMOS implementation of the processing element, realized with a mixed approach that uses both standard cells and custom blocks, allow maximum operating clock frequency over 21 MHz.
|Titolo:||Evaluation of a bit-serial ASIC chip for SAR processing|
|Data di pubblicazione:||1991|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1016/0165-6074(91)90018-O|
|Appare nelle tipologie:||1.1 Articolo in rivista|