A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A - Part II: Dynamic Analysis

In this paper we improve the semi-empirical compact model for CNTFETs, already proposed by us, considering both the quantum capacitance effects and the sub-threshold currents in order to carry out dynamic analysis of basic digital circuits. To verify the validity of the obtained results, they are compared with those of Wong model. Our model may be easily implemented both in SPICE and in Verilog-A, obtaining, in this last case, the development time in writing the model shorter, the simulation run time much shorter and the software much more concise and clear than Wong model.