Modelling and simulation of Sigma-Delta ADC in VHDL-AMS

Due to the high integration density of the modern electronic circuits, the behavioural modelling is necessary to predict the performace of systems. Adopting different hardware description languages, various levels of abstraction in modelling systems are possible, such as system level, algorithm description, functional blocks and gate-level net list. In this paper, the building blocks of Sigma - Delta converters are modelled using the VHDL-AMS language and its performance are evaluated