In this paper an integrated circuit (IC) design of the fractional order proportional-integral-derivative (PID) controller is proposed. The development of the IC device is realized in Cadence environment, using the switched capacitors (SC) technology in order to reduce the area on the silicon wafer and to improve the electrical controllability. In order to obtain transfer functions that describe the fractional order of the differ-integral operator it is necessary to use interpolation methods, in particular, the choice in this work has fallen on the Oustaloup interpolation. This procedure is aimed at implementing a series of pole-zero blocks that approximate the non-integer order. The realized approach is able to guarantee a good approximation of the fractional order PID and simultaneously propose a detailed circuit analysis of the influence of the non-idealities, in particular the phenomenon of warping. This takes into account the distortion introduced by the s-domain to the z-domain transition, acting on the positions of poles and zeros, especially those at a higher frequency. Time and frequency domain result tests confirm the feasibility and reliability of the SC implementation.
|Titolo:||Integrated technology fractional order proportional-integral-derivative design|
|Data di pubblicazione:||2014|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1177/1077546313487939|
|Appare nelle tipologie:||1.1 Articolo in rivista|