A new solution to improve the testability of high resolution SD Analogue to Digital Converters (SD ADC’s) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, fourth order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques. If only SNR, THD and gain of the SD ADC are evaluated with the new proposed method the test time is already reduced by 20%.
|Titolo:||Testing high resolution ΣΔ ADC's by using the quantizer input as test access|
|Data di pubblicazione:||2005|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1016/j.mejo.2005.03.004|
|Appare nelle tipologie:||1.1 Articolo in rivista|