Analysis of the substrate noise injection/coupling effects in an integrated DC-DC converter

The impact of substrate noise on the analog and RF performance is one of the most serious drawbacks of single-chip integration. In this paper the substrate noise effects due to the integration of a DC-DC converter into a 0.13μm RF CMOS technology integrated circuit have been investigated. The noise performance of the structure has been evaluated by simulations for providing designers with guidelines to improve noise isolation. In this paper,the dependence of substrate noise coupling on DRIFTMOS technological process, physical separation distance, floorplanning and guarding structure is fully described. Moreover, the analysis shows the necessity to modellize guarding structures in sub-micron technologies to prevent noise coupling during the design stage.