Static and Dynamic Analysis of CNTFET logic gates in Verilog-A

In this chapter we use our compact semi-empirical CNTFET model, examined in the previous chapters, in order to carry out, at first, static analysis of basic digital circuits. Then we consider in our model both the quantum capacitance effects and the sub-threshold currents to carry out also dynamic analysis of the examined CNTFET logic gates, implemented in complementary technology with both n-FETs and p-FETs on the same substrate, using MOSFET-like CNTFETs. To verify, in both cases, the validity of the obtained results, they are compared with those of Wong model of Stanford University. In particular our model may be easily implemented both in SPICE and in Verilog-A, obtaining, in this last case, the development time in writing the model shorter, the simulation run time much shorter and the software much more concise and clear than the Wong model.