The aim of this paper is to introduce a compact model for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) implemented in Verilog-A to assure easy integration with electrical circuit simulators. It takes into account the effects of voltage-dependent perpendicular magnetic anisotropy, temperature-dependent parameters, thermal heating/cooling, MTJ process variations, and the spin-torque asymmetry of the Slonczewski spin-polarization function in the switching process. This translates into a comprehensive modeling that was adopted to investigate the writing performance under voltage scaling of a 256Ã256 STT- magnetic random access memory array implemented at three different technology nodes. Obtained results show that scaling from 30- to 20-nm node allows a write energy saving of about 43%, while the supply voltage that assures the minimum-energy write operation increases.
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs / De Rose, Raffaele; Lanuzza, Marco; D'Aquino, Massimiliano; Carangelo, Greta; Finocchio, Giovanni; Crupi, Felice; Carpentieri, Mario. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - 64:10(2017), pp. 4346-4353. [10.1109/TED.2017.2734967]
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs
Carpentieri, Mario
2017-01-01
Abstract
The aim of this paper is to introduce a compact model for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) implemented in Verilog-A to assure easy integration with electrical circuit simulators. It takes into account the effects of voltage-dependent perpendicular magnetic anisotropy, temperature-dependent parameters, thermal heating/cooling, MTJ process variations, and the spin-torque asymmetry of the Slonczewski spin-polarization function in the switching process. This translates into a comprehensive modeling that was adopted to investigate the writing performance under voltage scaling of a 256Ã256 STT- magnetic random access memory array implemented at three different technology nodes. Obtained results show that scaling from 30- to 20-nm node allows a write energy saving of about 43%, while the supply voltage that assures the minimum-energy write operation increases.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
