Design of a multi-channel read-out ASIC for gas electron multiplier detectors

A 32-channel ASIC has been designed and fabricated in a standard 0.35 μm CMOS technology for the read-out of Gas Electron Multiplier detectors to be used for beam monitoring in hadron therapy applications. Each analog channel is based on the classic CSA+shaper architecture, followed by a peak detector which works as an analog memory during the read-out phase. An analog multiplexer routes the outputs of the peak detectors towards an on-board 8-bit subranging ADC. The ASIC is self-Triggered by a signal generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs of the channels with a programmable threshold voltage. The chip includes also a digital part, which allows managing in autonomous way the read-out procedure, in sparse or serial mode, the A/D conversion and the configuration of the programmable features, via a standard SPI interface. A 100 Mbit/s LVDS serial link is used for data communication. Preliminary characterization results show that the non-linearity error is limited to 5% in a dynamic range of about 70 fC and the time jitter of the trigger signal, generated in response to an injected charge of 60 fC, is close to 200 ps.