A 32-channel ASIC has been designed and fabricated in a standard 0.35 μm CMOS technology for the read-out of Gas Electron Multiplier detectors to be used for beam monitoring in hadron therapy applications. Each analog channel is based on the classic CSA+shaper architecture, followed by a peak detector which works as an analog memory during the read-out phase. An analog multiplexer routes the outputs of the peak detectors towards an on-board 8-bit subranging ADC. The ASIC is self-Triggered by a signal generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs of the channels with a programmable threshold voltage. The chip includes also a digital part, which allows managing in autonomous way the read-out procedure, in sparse or serial mode, the A/D conversion and the configuration of the programmable features, via a standard SPI interface. A 100 Mbit/s LVDS serial link is used for data communication. Preliminary characterization results show that the non-linearity error is limited to 5% in a dynamic range of about 70 fC and the time jitter of the trigger signal, generated in response to an injected charge of 60 fC, is close to 200 ps.

Design of a multi-channel read-out ASIC for gas electron multiplier detectors / Ciciriello, Fabio; Corsi, Francesco; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, Cristoforo; Matarrese, Gianvito; Ranieri, A.. - (2017), pp. 85-89. (Intervento presentato al convegno 7th International Workshop on Advances in Sensors and Interfaces, IWASI 2017 tenutosi a Vieste, Italy nel June 15-16, 2017) [10.1109/IWASI.2017.7974223].

Design of a multi-channel read-out ASIC for gas electron multiplier detectors

Ciciriello, Fabio;Corsi, Francesco;Marzocca, Cristoforo;Matarrese, Gianvito;
2017-01-01

Abstract

A 32-channel ASIC has been designed and fabricated in a standard 0.35 μm CMOS technology for the read-out of Gas Electron Multiplier detectors to be used for beam monitoring in hadron therapy applications. Each analog channel is based on the classic CSA+shaper architecture, followed by a peak detector which works as an analog memory during the read-out phase. An analog multiplexer routes the outputs of the peak detectors towards an on-board 8-bit subranging ADC. The ASIC is self-Triggered by a signal generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs of the channels with a programmable threshold voltage. The chip includes also a digital part, which allows managing in autonomous way the read-out procedure, in sparse or serial mode, the A/D conversion and the configuration of the programmable features, via a standard SPI interface. A 100 Mbit/s LVDS serial link is used for data communication. Preliminary characterization results show that the non-linearity error is limited to 5% in a dynamic range of about 70 fC and the time jitter of the trigger signal, generated in response to an injected charge of 60 fC, is close to 200 ps.
2017
7th International Workshop on Advances in Sensors and Interfaces, IWASI 2017
978-1-5090-6707-7
Design of a multi-channel read-out ASIC for gas electron multiplier detectors / Ciciriello, Fabio; Corsi, Francesco; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, Cristoforo; Matarrese, Gianvito; Ranieri, A.. - (2017), pp. 85-89. (Intervento presentato al convegno 7th International Workshop on Advances in Sensors and Interfaces, IWASI 2017 tenutosi a Vieste, Italy nel June 15-16, 2017) [10.1109/IWASI.2017.7974223].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11589/116728
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