Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

Aprototypeofanew-generationreadoutASICtargetingHigh-Luminosity(HL)LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 × 64 pixels with 50 µm × 50 µm pixel size embeddingtwodifferentarchitecturesofanalogfront-endsworkinginparallel. Thefinallayoutof thechipwassubmittedandacceptedforfabricationonJuly2016. Chipswerereceivedbackfrom the foundry on October 2016 and successfully characterized. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). First samplechipshavebeenalsobump-bondedto3DsensorsprovidedbyTrentoFBKandpreliminary characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre- and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology.