This paper presents a framework for the systematic design of inductor-less regulated cascode (RGC) stages. Targeting high-speed fiber optic data receiver front-ends, the technique reported combines the symbolic solution of the small-signal model of the RGC and the use of gm/ID based lookup tables to efficiently explore and optimize the resulting design space. A practical design is discussed and implemented in a 180 nm six-metal-layer CMOS process with 1.8V supply. The accuracy and viability of the proposed approach is validated through circuit simulation.
A systematic design approach for nanoscale inductor-less regulated cascode stages / Talarico, C.; D'Amato, G.; Avitabile, G.; Piccinni, G.; Coviello, G.. - (2016), pp. 1-5. (Intervento presentato al convegno 29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016 tenutosi a Belo Horizonte, Brazil nel 29 August - 3 September 2016) [10.1109/SBCCI.2016.7724057].
A systematic design approach for nanoscale inductor-less regulated cascode stages
D'Amato, G.;Avitabile, G.;Piccinni, G.;Coviello, G.
2016-01-01
Abstract
This paper presents a framework for the systematic design of inductor-less regulated cascode (RGC) stages. Targeting high-speed fiber optic data receiver front-ends, the technique reported combines the symbolic solution of the small-signal model of the RGC and the use of gm/ID based lookup tables to efficiently explore and optimize the resulting design space. A practical design is discussed and implemented in a 180 nm six-metal-layer CMOS process with 1.8V supply. The accuracy and viability of the proposed approach is validated through circuit simulation.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
