This paper presents a framework for the systematic design of inductor-less regulated cascode (RGC) stages. Targeting high-speed fiber optic data receiver front-ends, the technique reported combines the symbolic solution of the small-signal model of the RGC and the use of gm/ID based lookup tables to efficiently explore and optimize the resulting design space. A practical design is discussed and implemented in a 180 nm six-metal-layer CMOS process with 1.8V supply. The accuracy and viability of the proposed approach is validated through circuit simulation.
|Titolo:||A systematic design approach for nanoscale inductor-less regulated cascode stages|
|Data di pubblicazione:||2016|
|Nome del convegno:||29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1109/SBCCI.2016.7724057|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|