In this paper we simulate the effects of temperature in CNTFETs-based digital circuits, enhancing a compact model, already proposed by us, in which the temperature variation in the drain current equation and in energy bandgap is considered. Using ADS software, we simulate some basic digital circuits including NOT, NOR and NAND logic gates. In particular we observe how typical quantities like noise margin and static power vary in relation to temperature and supply voltage. At last we find that generally the most critical working condition is at high temperatures with some exceptions depending on supply voltage applied.

Effects of Temperature in CNTFET-Based Design of Digital Circuits / Gelao, G.; Marani, R.; Perri, A. G.. - In: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY. - ISSN 2162-8769. - STAMPA. - 7:3(2018), pp. 41-48. [10.1149/2.0261803jss]

Effects of Temperature in CNTFET-Based Design of Digital Circuits

G. Gelao;R. Marani
Methodology
;
A. G. Perri
Conceptualization
2018-01-01

Abstract

In this paper we simulate the effects of temperature in CNTFETs-based digital circuits, enhancing a compact model, already proposed by us, in which the temperature variation in the drain current equation and in energy bandgap is considered. Using ADS software, we simulate some basic digital circuits including NOT, NOR and NAND logic gates. In particular we observe how typical quantities like noise margin and static power vary in relation to temperature and supply voltage. At last we find that generally the most critical working condition is at high temperatures with some exceptions depending on supply voltage applied.
2018
Effects of Temperature in CNTFET-Based Design of Digital Circuits / Gelao, G.; Marani, R.; Perri, A. G.. - In: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY. - ISSN 2162-8769. - STAMPA. - 7:3(2018), pp. 41-48. [10.1149/2.0261803jss]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11589/124047
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