A digital to analog converter for slow control of pixel front-end chip has been designed in a standard 0.35 mum CMOS technology to prove the effectiveness of the chosen circuit structures for this application. The DAC provides a total output current variation of about 13 muA with 8 bits of accuracy (LSB congruent to 51nA). The circuit is based on a PMOS current bank, since an "enclosed" NMOS of reasonable size would operate in weak inversion for these current levels and would hence be unsuitable for accurate current sources. The bit value determines whether the corresponding current is switched to the output or sent to ground. The occupied area is about 300 mum x 300 mum and total power dissipation is 85 muW. The results of the test measurements performed on 31 fabricated prototypes show that statistical fluctuations of the output current due to mismatch are negligible compared to the desired accuracy for all the input configurations. Results of X-ray irradiation tests carried out at the CERN facility will be also presented.
|Titolo:||Design and Characterization of a DAC for the Slow Control of the Pixel Chip|
|Data di pubblicazione:||2000|
|Nome del convegno:||Sixth Workshop on Electronics for LHC Experiments, Cracovia, Polonia|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|