The main purpose of this paper is to review the framework behind direct digital synthesizer phase-locked loops (DDS-PLLs), as well as to provide a set of novel techniques that can be used during the development and the deployment of phased arrays based on local oscillator (LO) phase shifting approaches. A beam steering transmitter prototype employing our revised DDS-PLL architecture and the experimental results obtained during its characterization are presented. The main contribution of the proposed implementation consists in showing that the output phase increments of the DDS-PLL are unaffected by the frequency multiplication operated by the PLL. The proposed prototype is centered at 3.350 GHz and allows to independently set the phase of its four LOs at 2.453 GHz with an 8-bit resolution. The DDS-PLL architecture is frequency-independent, and the modular structure of its phase control units allows to achieve different phase resolutions with a very small redesign effort.
DDS-PLL Phase Shifter Architectures for Phased Arrays: Theory and Techniques / D'Amato, Giulio; Avitabile, Gianfranco; Coviello, Giuseppe; Talarico, Claudio. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 7:(2019), pp. 8626092.19461-8626092.19470. [10.1109/ACCESS.2019.2895388]
DDS-PLL Phase Shifter Architectures for Phased Arrays: Theory and Techniques
D'Amato, Giulio;Avitabile, Gianfranco;Coviello, Giuseppe;
2019-01-01
Abstract
The main purpose of this paper is to review the framework behind direct digital synthesizer phase-locked loops (DDS-PLLs), as well as to provide a set of novel techniques that can be used during the development and the deployment of phased arrays based on local oscillator (LO) phase shifting approaches. A beam steering transmitter prototype employing our revised DDS-PLL architecture and the experimental results obtained during its characterization are presented. The main contribution of the proposed implementation consists in showing that the output phase increments of the DDS-PLL are unaffected by the frequency multiplication operated by the PLL. The proposed prototype is centered at 3.350 GHz and allows to independently set the phase of its four LOs at 2.453 GHz with an 8-bit resolution. The DDS-PLL architecture is frequency-independent, and the modular structure of its phase control units allows to achieve different phase resolutions with a very small redesign effort.File | Dimensione | Formato | |
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