This paper shows how Carbon Nanotubes FETs (CNTFETs) can be used in the design of ternary logic gates, which is a promising alternative to the conventional binary logic design. In particular we propose the design of NOR/NAND gates and of a Decoder, all in ternary logic. The main novelty is that in this paper all simulations are performed in Verilog-A, avoiding so the problems presented in SPICE. At last we show that the proposed ternary logic gates consume significantly lower power and delay time than the previous CNTFET gates implementations.

A Design Technique of CNTFET-Based Ternary Logic Gates in Verilog-A / Marani, Roberto; Perri, Anna Gina. - In: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY. - ISSN 2162-8769. - STAMPA. - 8:4(2019), pp. 45-52. [10.1149/2.0181904jss]

A Design Technique of CNTFET-Based Ternary Logic Gates in Verilog-A

Roberto Marani
Software
;
Anna Gina Perri
Conceptualization
2019-01-01

Abstract

This paper shows how Carbon Nanotubes FETs (CNTFETs) can be used in the design of ternary logic gates, which is a promising alternative to the conventional binary logic design. In particular we propose the design of NOR/NAND gates and of a Decoder, all in ternary logic. The main novelty is that in this paper all simulations are performed in Verilog-A, avoiding so the problems presented in SPICE. At last we show that the proposed ternary logic gates consume significantly lower power and delay time than the previous CNTFET gates implementations.
2019
A Design Technique of CNTFET-Based Ternary Logic Gates in Verilog-A / Marani, Roberto; Perri, Anna Gina. - In: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY. - ISSN 2162-8769. - STAMPA. - 8:4(2019), pp. 45-52. [10.1149/2.0181904jss]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11589/171722
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