A Design Technique of CNTFET-Based Ternary Logic Gates in Verilog-A

This paper shows how Carbon Nanotubes FETs (CNTFETs) can be used in the design of ternary logic gates, which is a promising alternative to the conventional binary logic design. In particular we propose the design of NOR/NAND gates and of a Decoder, all in ternary logic. The main novelty is that in this paper all simulations are performed in Verilog-A, avoiding so the problems presented in SPICE. At last we show that the proposed ternary logic gates consume significantly lower power and delay time than the previous CNTFET gates implementations.