In this paper we present the design of CNTFETs-based ternary logic gates, which are a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. In particular we propose the design of a 3 × 1 Mux and a D flip flop, all in ternary logic. Simulations are performed in Verilog-A, using a CNTFET model already proposed by us. The obtained results are encouraging and show that this approach is suitable for high frequency signals.

Three-Levels Logic Gates Design Based on CNTFETs / Gelao, Gennaro; Marani, Roberto; Perri, Anna Gina. - In: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY. - ISSN 2162-8769. - STAMPA. - 8:8(2019), pp. 67-70. [10.1149/2.0031908jss]

Three-Levels Logic Gates Design Based on CNTFETs

Gennaro Gelao
Software
;
Roberto Marani
Conceptualization
;
Anna Gina Perri
Methodology
2019-01-01

Abstract

In this paper we present the design of CNTFETs-based ternary logic gates, which are a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. In particular we propose the design of a 3 × 1 Mux and a D flip flop, all in ternary logic. Simulations are performed in Verilog-A, using a CNTFET model already proposed by us. The obtained results are encouraging and show that this approach is suitable for high frequency signals.
2019
Three-Levels Logic Gates Design Based on CNTFETs / Gelao, Gennaro; Marani, Roberto; Perri, Anna Gina. - In: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY. - ISSN 2162-8769. - STAMPA. - 8:8(2019), pp. 67-70. [10.1149/2.0031908jss]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11589/175667
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