An automatic optimization technique of the SIV layout to improve the thermal design of power GaAs MESFETs

In this paper an automatic procedure is proposed to extract optimal layout parameters for a SIV FET structure of MESFET oriented to the minimization of the device thermal resistance. These parameters are gate length, gate width, number of gates, gate to gate spacing, die thickness and the optimal heat sink temperature. The formula expressing the device thermal resistance as function of these parameters accounts for the dependence of the thermal conductivity of gallium arsenide on temperature and doping density. The initial values of the design parameters necessary to run the minimization procedure are determined from the other design MESFET specifications as the maximum drain current, the frequency performance and so on. In this way it is possible to design a MESFET layout that allows to obtain a device thermal resistance as low as possible compatibly with other design specifications.