An 8-bit Analog-to-Digital Converter (ADC), suitable to be integrated in multi-channel ASICs for the read-out of SiPM arrays, has been designed in a standard 0.35µm CMOS process. The circuit implements two 8-bit interleaved ADCs with a two-step flash architecture. Each ADC has a sub-ranging mode of operation, and the overall frequency of conversion is of 20MHz. Clock boosting techniques have been exploited to improve the performance of the transmission gates used as switches and a pre-coarse conversion phase has been introduced to improve the conversion accuracy for signals close to the limits of the input dynamic range. Much care has been devoted to the design of the resistor ladder used to generate the voltage references for the comparators. In particular a statistical approach has been adopted to optimize the standard deviations of the voltage references due to resistor mismatch. A test chip containing a prototype of the ADC has been manufactured and the first characterization measurements are here presented and discussed.
An 8-bit, Two-step Embedded ADC for a SiPM Read-out Chip / Corsi, Francesco; Marzocca, Cristoforo; Matarrese, Gianvito; Foresta, M.; Argentieri, A.; Del Guerra, A.. - (2010), pp. 1377-1381. (Intervento presentato al convegno 2010 IEEE Nuclear Science Symposium, Medical Imaging Conference, and 17th International Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors tenutosi a Knoxville, TN nel October 30 - November 6, 2010) [10.1109/NSSMIC.2010.5873996].
An 8-bit, Two-step Embedded ADC for a SiPM Read-out Chip
CORSI, Francesco;MARZOCCA, Cristoforo;MATARRESE, Gianvito;
2010-01-01
Abstract
An 8-bit Analog-to-Digital Converter (ADC), suitable to be integrated in multi-channel ASICs for the read-out of SiPM arrays, has been designed in a standard 0.35µm CMOS process. The circuit implements two 8-bit interleaved ADCs with a two-step flash architecture. Each ADC has a sub-ranging mode of operation, and the overall frequency of conversion is of 20MHz. Clock boosting techniques have been exploited to improve the performance of the transmission gates used as switches and a pre-coarse conversion phase has been introduced to improve the conversion accuracy for signals close to the limits of the input dynamic range. Much care has been devoted to the design of the resistor ladder used to generate the voltage references for the comparators. In particular a statistical approach has been adopted to optimize the standard deviations of the voltage references due to resistor mismatch. A test chip containing a prototype of the ADC has been manufactured and the first characterization measurements are here presented and discussed.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
