The paper describes the FPGA implementation of a novel TDOA distance evaluation algorithm that combine the characteristics of an OFDM symbol with the properties of the Zadoff-Chu mathematical sequences. The distance evaluation system has been validated in presence of severe multipath interference and allows to achieve an accuracy that is always within 1.2cm of the target position. The algorithm is implemented using the FPGA (Cyclone IV-E EP4CE115F29C8L Cyclone IV-E) available on the Altera's DE2-115 development board. The implementation requires about 120k bit of memory and less than 40k logic elements (of which about 30k are registers).
Implementation of a Real-Time Distance Evaluation Algorithm for Wireless Localization Systems / Piccinni, G.; Avitabile, G.; Coviello, G.; Talarico, C.. - STAMPA. - (2019), pp. 993-996. (Intervento presentato al convegno 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019 tenutosi a Dallas, TX nel August 4-7, 2019) [10.1109/MWSCAS.2019.8884966].
Implementation of a Real-Time Distance Evaluation Algorithm for Wireless Localization Systems
G. Piccinni;G. Avitabile;G. Coviello;
2019-01-01
Abstract
The paper describes the FPGA implementation of a novel TDOA distance evaluation algorithm that combine the characteristics of an OFDM symbol with the properties of the Zadoff-Chu mathematical sequences. The distance evaluation system has been validated in presence of severe multipath interference and allows to achieve an accuracy that is always within 1.2cm of the target position. The algorithm is implemented using the FPGA (Cyclone IV-E EP4CE115F29C8L Cyclone IV-E) available on the Altera's DE2-115 development board. The implementation requires about 120k bit of memory and less than 40k logic elements (of which about 30k are registers).I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
