Implementing a Tuning Algorithm for Continuous-time Filters in a Digital Environment

Continuous-time filters, usually employed in telecommunication applications, require a tuning system to align their frequency response. Here we suggest a digital implementation of a recently proposed tuning approach; the technique is based on the application of a pseudo-random input testing pattern signal and on the evaluation of a few samples of the input-output cross-correlation function. Basically, the key advantage of this technique is related to the on-chip implementation of all the tuning steps in the digital domain, from the input pseudo-random pattern generation to the filter output sampling and cross-correlation evaluation. Moreover, the digital circuitry required is simple and entails little area overhead. We report the first experimental results, performed to validate the effectiveness of the technique implementation for the tuning of a baseband multi-standard filter. The digital circuitry required to both generate the input stimuli and adjust the filter performance has been implemented by means of an FPGA. The measurements confirm most of the simulation results and the digital implementation of the algorithm shows its robustness against practical operating conditions and noise.