The inductive fault analysis approach has been used to study the circuit behavior of the regular array of an electrical programmable logic device. The analysis is based on the knowledge of the chip layout and fabrication technology and takes into account only single localized defects related to the photolithographic process. A list of physical changes in the cell layout has been derived and interpreted at circuit level. Functional faults have been distinguished from parametric degradations and the validity of the stuck-at and cross-point fault models has been assessed
Modeling the Electrical Behavior of an EPLD Cell Array, in the Presence of Lithography Induced Spot Defects / Corsi, F.; De Venuto, D; Martino, S; Morandi, C. - STAMPA. - (1991), pp. 521-525. (Intervento presentato al convegno 5th European Computer Conference on Advanced Computer Technology, Reliable Systems and Applications, CompEuro 91 tenutosi a Bologna, Italy nel May 13-16, 1991) [10.1109/CMPEUR.1991.257441].
Modeling the Electrical Behavior of an EPLD Cell Array, in the Presence of Lithography Induced Spot Defects
Corsi F.;De Venuto D;
1991-01-01
Abstract
The inductive fault analysis approach has been used to study the circuit behavior of the regular array of an electrical programmable logic device. The analysis is based on the knowledge of the chip layout and fabrication technology and takes into account only single localized defects related to the photolithographic process. A list of physical changes in the cell layout has been derived and interpreted at circuit level. Functional faults have been distinguished from parametric degradations and the validity of the stuck-at and cross-point fault models has been assessedI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
