An application of the Petri net formal model, augmented by inserting the notion of time, to the analysis of the time behavior of digital circuits, is presented. The modeling, simulation, and performance evaluation are examined. The results show that the Petri net model is very useful in the logic simulation of VLSI circuits as it transforms time into space (memory) complexity. Examples illustrate the way in which Petri nets can be used for evaluating the maximum time performance of a digital network.
Evaluation of the Behaviour of Digital Circuits by Timed Petri Nets / Castagnolo, B.; Corsi, F.. - STAMPA. - (1986), pp. 1004-1007. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems, ISCAS 1986 tenutosi a San Jose, CA nel May 5-7, 1986).
Evaluation of the Behaviour of Digital Circuits by Timed Petri Nets
Castagnolo, B.;Corsi, F.
1986-01-01
Abstract
An application of the Petri net formal model, augmented by inserting the notion of time, to the analysis of the time behavior of digital circuits, is presented. The modeling, simulation, and performance evaluation are examined. The results show that the Petri net model is very useful in the logic simulation of VLSI circuits as it transforms time into space (memory) complexity. Examples illustrate the way in which Petri nets can be used for evaluating the maximum time performance of a digital network.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
