Interfacing a SiPM to a Current-mode Front-end: Effects of the Coupling Inductance

The design of front-end electronics for SiPM detectors poses some peculiar constraints which call for dedicated architectures that may remarkably differ from the commonly used ones for other solid state detectors. In particular, present day SiPM’s may have a number of microcells as high as 90,000. This may pose serious problems in terms of dynamic range of the output signal, especially when low voltage technologies are employed to implement the FE. Besides that, SiPM’s are inherently high speed devices characterized by large equivalent capacitance CDET. All the above characteristics indicate a current mode architecture as the most suitable one to interface this kind of devices. In the past several different topologies have been proposed in the literature most of them aiming at realizing the lowest possible value of input resistance, Rin, in the perspective of limiting the time constant in = RinCDET associated to the input node of the amplifier, which is usually deemed to be the dominant parameter affecting the dynamic performance of the FE. In this contribution we show that this is not the case in real situations and that there is an optimum range of values for the input resistance in dependence of the particular SiPM and of the interconnection parasitics, thus avoiding the need of realizing arbitrarily low values of input resistance that would also imply unnecessary high power dissipation and additional electronic noise, due to the high bias currents required in the input stage of the preamplifier. The results of the study, performed on a handly 2nd order SiPM model, are confirmed by both circuit simulations on a more accurate 4th order model and by lab experiments on commercially available devices.