In this paper we analyze an application of CNTFET in the design of NOT gate, in which parasitic elements of interconnection lines are considered. At first we study the time domain analysis of NOT gate without to consider the parasitic elements of interconnection lines, in order to compare the obtained results with those in which the parasitic elements are considered, showing how they limit the high-speed performances of CNTs.
A Procedure to Analyze a CNTFET-based NOT Gate with Parasitic Elements of Interconnection Lines / Marani, Roberto; Perri, Anna Gina. - In: INTERNATIONAL JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY. - ISSN 0974-3081. - STAMPA. - 17:3(2021), pp. 161-171.
A Procedure to Analyze a CNTFET-based NOT Gate with Parasitic Elements of Interconnection Lines
Anna Gina Perri
2021-01-01
Abstract
In this paper we analyze an application of CNTFET in the design of NOT gate, in which parasitic elements of interconnection lines are considered. At first we study the time domain analysis of NOT gate without to consider the parasitic elements of interconnection lines, in order to compare the obtained results with those in which the parasitic elements are considered, showing how they limit the high-speed performances of CNTs.| File | Dimensione | Formato | |
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IJNN_Volume 17_Issue 3_Pages 161-171.pdf
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