The paper describes a 10-bits three channels phase shifter in 0.35 μm SiGe BiCMOS technology. The chip was designed for control an Active Electronically Phase Array (AESA). It is composed by a digital Phase Control Block (PCB) which generates square waves with a minimum phase shift of 0.3515° and an output frequency of 1.953MHz; the system clock is 2GHz. Besides the PLLs and the VCOs are external components in order to validate the frequency-independence of the architecture proposed. As expected from the simulations, the maximum phase error is less than 0.1° and the rms phase error is less than 0.06°. The complete systems at 2.45GHz with almost the same maximum phase error and rms confirm the validity of the architecture
A 10-bits three channels phase shifter integrated circuit for Active Electronic Scanned Array applications
Coviello;Avitabile G;Margiotta N
2015-01-01
Abstract
The paper describes a 10-bits three channels phase shifter in 0.35 μm SiGe BiCMOS technology. The chip was designed for control an Active Electronically Phase Array (AESA). It is composed by a digital Phase Control Block (PCB) which generates square waves with a minimum phase shift of 0.3515° and an output frequency of 1.953MHz; the system clock is 2GHz. Besides the PLLs and the VCOs are external components in order to validate the frequency-independence of the architecture proposed. As expected from the simulations, the maximum phase error is less than 0.1° and the rms phase error is less than 0.06°. The complete systems at 2.45GHz with almost the same maximum phase error and rms confirm the validity of the architectureI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
