In this paper we review a procedure to design a full adder circuit based on CNTFET technology. In particular the proposed circuit is based on NAND and NOT logic gates. Using ADS software, we describe the procedure to determine the velocity, delay and power delay product (PDP), showing moreover the improvements obtained with CNTFET technology compared to CMOS one.

Review-Design of a Novel Full Adder Circuit based on CNTFET Technology

Anna Gina Perri
Methodology
2022

Abstract

In this paper we review a procedure to design a full adder circuit based on CNTFET technology. In particular the proposed circuit is based on NAND and NOT logic gates. Using ADS software, we describe the procedure to determine the velocity, delay and power delay product (PDP), showing moreover the improvements obtained with CNTFET technology compared to CMOS one.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11589/239344
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