In this paper we review a procedure to design a full adder circuit based on CNTFET technology. In particular the proposed circuit is based on NAND and NOT logic gates. Using ADS software, we describe the procedure to determine the velocity, delay and power delay product (PDP), showing moreover the improvements obtained with CNTFET technology compared to CMOS one.
Review-Design of a Novel Full Adder Circuit based on CNTFET Technology / Marani, Roberto; Perri, Anna Gina. - In: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY. - ISSN 2162-8769. - 11:5(2022). [10.1149/2162-8777/ac6d78]
Review-Design of a Novel Full Adder Circuit based on CNTFET Technology
Roberto MaraniSoftware
;Anna Gina Perri
Methodology
2022-01-01
Abstract
In this paper we review a procedure to design a full adder circuit based on CNTFET technology. In particular the proposed circuit is based on NAND and NOT logic gates. Using ADS software, we describe the procedure to determine the velocity, delay and power delay product (PDP), showing moreover the improvements obtained with CNTFET technology compared to CMOS one.File in questo prodotto:
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